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      Samsung Electronics Updates Next-Generation DRAM Roadmap with B1b Integration

      Samsung Electronics has revised its next-generation DRAM strategy by officially incorporating the previously project-based B1b into its roadmap, designating it as the first DRAM D0a below 10 nanometers. This adjustment comes as the company aims to enhance the introduction of advanced packaging technologies in general DRAM. The previous designation of D0a referred to vertical transistor DRAM, which is now classified separately as D0a-V.

      The B1b technology will manufacture storage cells and peripheral driver circuits on distinct wafers before bonding them together, utilizing wafer-to-wafer hybrid bonding and copper interconnects for direct connections. Currently, the commercialized DRAM is 1c, representing the 6th generation at the 10 nanometer level, while the upcoming 1d will be the 7th generation, effectively marking the last of the 10 nanometer products. The transition to vertical transistors aims to reduce cell area but presents challenges in development due to high aspect ratio etching and leakage current issues.

      Samsung is also exploring the application of B1b for the 8th generation high bandwidth memory, HBM5, which is projected to be mass-produced around 2029. HBM5 is anticipated to enhance operating speeds by over 50% compared to its predecessor, HBM4E. Industry analysts estimate that D0a DRAM based on B1b will be commercially available within two years, with specific investment schedules for mass production expected to be finalized by mid-next year.

      © 2026 KLEA News. All Rights Reserved. This article is provided for informational purposes only. It is not offered or intended to be used as legal, tax, investment, financial, or other advice.

      Source: KLEA News

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